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| NCP1580 Low Voltage Synchronous Buck Controller The NCP1580 is a voltage mode PWM controller designed to operate from a 5.0 V or 12 V supply and produce an output voltage as low as 0.8 V. This 8-pin device provides an optimal level of integration to reduce size and cost of the power supply. The NCP1580 has a fixed 350 kHz oscillator and soft-start function. The NCP1580 provides a 1.5 A floating gate driver design to drive N-Channel MOSFETs in a synchronous configuration. Adaptive non-overlap circuitry reduces switching losses by preventing simultaneous conduction of both outputs. Protection features include thermal shutdown and undervoltage lockout (UVLO). The NCP1580 is available in an 8-pin SOIC package. Features http://onsemi.com MARKING DIAGRAM 8 8 1 SOIC-8 D SUFFIX CASE 751 1 A L Y W = Assembly Location = Wafer Lot = Year = Work Week 1580 ALYW * * * * * * * * * * * * * * * * * * * Input Voltage Range from 4.5 V to 13.2 V 350 kHz Internal Oscillator Boost Pin Operates to 26.5 V Voltage Mode PWM Control 0.8 V $1.5% Internal Reference Voltage Adjustable Output Voltage Internal Soft-Start Internal 1.5 A Gate Drivers Adaptive Non-Overlap Circuit 90% Max Duty Cycle Input UVLO Overtemperature Protection Fully Specified over -40C to 85C Pb-Free Package is Available Graphics Cards Desktop Computers Servers/Networking DSP and FPGA Power Supply DC-DC Regulator Modules VIN PIN CONNECTIONS BST 1 TG 2 GND 3 BG 4 (Top View) 8 PHASE 7 COMP 6 FB 5 VCC ORDERING INFORMATION Device NCP1580DR2 NCP1580DR2G Package SOIC-8 SOIC-8 (Pb-Free) Shipping 2500/Tape & Reel 2500/Tape & Reel Applications For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. BST TG VOUT SWN VCC FB COMP BG GND Figure 1. Typical Application Diagram (c) Semiconductor Components Industries, LLC, 2005 1 January, 2005 - Rev. 4 Publication Order Number: NCP1580/D NCP1580 VIN RB751V40T10 2x 1500 mF NTD60N02R 4x 22 mF 1 mH MBR130LSFT1 VOUT 0.1 mF PHASE 10 nF 3.3 nF 15 k 1 mF 68.1 10 nF COMP FB VCC BST TG GND BG 2.2 NTD110N02R 2x 100 mF 2x 1800 mF 5.36 k 4.7 nF 20 k GND Figure 2. Application Diagram; 12 V Input, 1.0 V at 20 A Output FAULT Comparator + - Clock R Q S Error Amp + - + Ramp OSC POR OSC FAULT FAULT 1 2 8 BST TG PHASE OSC SS (VSS) + - 2V + - 2V VCC FB 6 COMP 7 0.8 V (VREF) TSD 4 3 BG GND VCC 5 FAULT Figure 3. Detailed Block Diagram http://onsemi.com 2 NCP1580 PIN FUNCTION DESCRIPTION Pin No. 1 Symbol BST Description Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the desired input voltage to this pin (cathode connected to BST pin). Connect a capacitor (CBST) between this pin and the PHASE pin. Typical values for CBST range from 0.1 mF to 1 mF. Ensure that CBST is placed near the IC. Top gate MOSFET driver pin. Connect this pin to the gate of the top N-Channel MOSFET. IC ground reference. All control circuits are referenced to this pin. Bottom gate MOSFET driver pin. Connect this pin to the gate of the bottom N-Channel MOSFET. Supply rail for the internal circuitry. Operating supply range is 4.5 V to 13.2 V. Decouple with a 1 mF capacitor to GND. Ensure that this decoupling capacitor is placed near the IC. This pin is the inverting input to the error amplifier. Use this pin in conjunction with the COMP pin to compensate the voltage-control feedback loop. Connect this pin to the output resistor divider (if used) or directly to Vout. Compensation Pin. This is the output of the error amplifier (EA) and the non-inverting input of the PWM comparator. Use this pin in conjunction with the FB pin to compensate the voltage-control feedback loop. This pin should not be shorted to ground to disable switching. Switch node pin. This is the reference for the floating top gate driver. Connect this pin to the source of the top MOSFET. A Schottky diode between this pin and ground is recommended to reduce negative transient voltages which is common in a power supply system. 2 3 4 5 6 TG GND BG VCC FB 7 COMP 8 PHASE ABSOLUTE MAXIMUM RATINGS Pin Name Main Supply Voltage Input Bootstrap Supply Voltage Input Switching Node (Bootstrap Supply Return) High-Side Driver Output (Top Gate) Low-Side Driver Output (Bottom Gate) Feedback COMP Symbol VCC BST PHASE TG BG FB COMP VMAX 15 V 30 V wrt/GND 15 V wrt/PHASE 30 V 30 V wrt/GND 15 V wrt/PHASE 15 V 5.5 V 5.5 V VMIN -0.3 V -0.3 V -0.7 V, t > 50 ns -2.0 V, t < 50 ns -0.3 V wrt/PHASE -0.3 V -0.3 V -0.3 V MAXIMUM RATINGS Rating Thermal Resistance, Junction-to-Case Operating Junction Temperature Range Operating Ambient Temperature Range Storage Temperature Range ESD Susceptibility Moisture Sensitivity Level Human Body Model Charge Device Model MSL Symbol RqJC TJ TA Tstg Value 45 -40 to 150 -40 to 85 -55 to +150 2.0 200 1 Unit C/W C C C kV V - Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. http://onsemi.com 3 NCP1580 ELECTRICAL CHARACTERISTICS (-40C < TA < 85C, -40C < TJ < 125C (Note 1), 4.5 V < VCC < 13.2 V, 4.5 V < BST < 26.5 V, CTG = CBG = 1.0 nF, for min/max values unless otherwise noted.) Characteristic Input Voltage Range Boost Voltage Range Supply Current Quiescent Supply Current Boost Quiescent Current Undervoltage Lockout UVLO Threshold UVLO Hysteresis Switching Regulator VFB Feedback Voltage, Control Loop in Regulation Oscillator Frequency Ramp-Amplitude Voltage Minimum Duty Cycle Maximum Duty Cycle Minimum Pulse Width Error Amplifier DC Gain Gain-Bandwidth Product Slew Rate FB Bias Current Gate Drivers TG Rise Time TG Fall Time BG Rise Time BG Fall Time TG Sink Current TG Source Current BG Sink Current BG Source Current PHASE falling to BG rising delay VCC = 12 V PHASE < 2.0 V BG > 2.0 V VCC = 12 V BG < 2.0 V TG > 2.0 V VCC = 12 V VTG = VBG = 2 0 V 2.0 (Note 2) ( ) Load = 1.0 nF VCC = 8.0 V - - - - - - - - - 6.0 15 6.0 6.0 1.0 1.5 1.5 1.5 30 15 30 15 15 - - - - 90 ns ns ns ns A A A A ns (Note 2 ) (Note 2) COMP_GND = 100 pF (Note 2) VFB = 1 V (Note 2) 70 8.0 2.0 - 80 10 4.0 0.1 - - - 1.0 dB MHz V/mS mA TA = 0 to 70C TA = -40 to 85C - - - - Static Operating (Note 2) 0.788 0.784 288 - - 85 50 0.800 - 350 1.1 0 90 100 0.812 0.816 412 - - 95 150 V kHz V % % nsec VCC Rising Edge - 3.85 - 4.2 0.5 - - V V VFB = 1.0 V, No Switching VCC = 13.2 V VFB = 1.0 V, No Switching - - 1.0 140 1.75 - mA mA Conditions - - Min 4.5 4.5 Typ - - Max 13.2 26.5 Unit V V BG falling to TG rising delay - 30 40 ns Internal Soft-Start Time Thermal Shutdown Overtemperature Trip Point (Note 2) - 160 - C - 1.0 2.0 3.0 ms 1. Specifications to -40C are guaranteed via correlation using standard statistical quality control (SQC), not tested in production. 2. Guaranteed by design, not tested in production. http://onsemi.com 4 NCP1580 TYPICAL CHARACTERISTIC CURVES 816 812 VREF, REFERENCE (mV) fSW, FREQUENCY (kHz) 808 804 800 796 792 788 784 -50 -25 0 25 50 75 100 125 150 410 400 390 380 370 360 350 340 330 320 310 300 290 -50 VCC = 12 V VCC = 5.0 V -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C) Figure 4. Reference Voltage (VREF) vs. Temperature 2.20 ICC, SUPPLY CURRENT (mA) tSS, SOFT-START TIME (ms) 2.15 2.10 2.05 2.00 1.95 1.90 1.85 1.80 -50 -25 0 25 50 75 100 125 150 VCC = 5.0 V 1.25 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 0.75 -50 Figure 5. Oscillator Frequency (fSW) vs. Temperature VCC = 12 V VCC = 5.0 V VCC = 12 V -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C) Figure 6. Soft-Start Time (tSS) vs. Temperature Figure 7. Quiescent Current (ICC) vs. Temperature (No Switching) 100 6.0 ICC, SUPPLY CURRENT (mA) 5.5 5.0 4.5 4.0 3.5 3.0 2.5 -50 -25 0 25 VCC = 5.0 V VCC = 8.0 V GAIN (dB) 100 125 150 VCC = 12 V 80 60 40 20 0 -20 -40 -60 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 50 75 TJ, JUNCTION TEMPERATURE (C) FREQUENCY (Hz) Figure 8. Quiescent Current (ICC) vs. Temperature (Switching) Figure 9. Error Amplifier http://onsemi.com 5 NCP1580 DETAILED OPERATING DESCRIPTION General The NCP1580 is an 8-pin PWM controller intended for DC-DC conversion from 5.0 V and 12 V buses. The NCP1580 has a 1.5 A internal floating gate driver circuit designed to drive N-Channel MOSFETs in a synchronous-rectifier buck topology. The internal floating gate driver simplifies design, improves performance, and minimizes board area. The output voltage of the converter can be precisely regulated down to 800 mV $ 1.5% when the VFB pin is tied to VOUT. The switching frequency, which is internally set to 350 kHz, and soft-start are completely integrated. The voltage error amplifier features a 10 MHz unity gain bandwidth and 4 V/msec slew rate for fast transient response. Duty Cycle and Maximum Pulse Width Limits Input Voltage Range (VCC and BST) The input voltage range for both VCC and BST is 4.5 V to 13.2 V with respect to GND and PHASE, respectively. Although BST is rated at 13.2 V with respect to PHASE, it can also tolerate 26.5 V with respect to GND. Normal Shutdown Behavior Normal shutdown occurs when the IC stops switching because the input supply reaches UVLO threshold. In this case, switching stops, the internal SS is discharged, and all GATE pins go low. The switch node enters a high impedance state and the output capacitors discharge through the load with no ringing on the output voltage. Internal Soft-Start In steady state DC operation, the duty cycle will stabilize at an operating point defined by the ratio of the input to the output voltage. The NCP1580 can achieve a 90% duty cycle. There is a built in off-time which ensures that the bootstrap supply is charged every cycle. The NCP1580, which is capable of a 100 nsec minimum pulse width (typ), can allow a 12 V to 1.0 V conversion at 350 kHz. The NCP1580 features an internal soft-start function, which reduces inrush current and overshoot of the output voltage. Figure 10 shows a typical soft-start sequence. Soft-start is achieved by ramping up the internal soft-start voltage (VSS) which is applied to the input of the error amplifier. This ramp is generated by applying 0.5 mA to a 100 pf capacitor for 1 msec on every fourth clock pulse. This sequence begins once VCC surpasses its UVLO threshold (see Figure 11). The typical soft-start time is 2 msec. The internal soft-start voltage is held low when the part is in UVLO. 4.2 V VCC 4.2 V 2 ms VCC VOUT TG UVLO Startup Normal Operation VSS CLK SS 1 mS 5 mV Figure 10. Normal Startup Figure 11. Achieving Internal Soft-Start http://onsemi.com 6 NCP1580 UVLO Undervoltage Lockout (UVLO) is provided to ensure that unexpected behavior does not occur when VCC is too low to support the internal rails and power the converter. For the NCP1580, the UVLO is set to ensure that the IC will start up when VCC reaches 4.2 V and shutdown when VCC drops below 3.7 V. This permits operation when converting from a 5.0 V input voltage. Thermal Shutdown The NCP1580 also provides Thermal Shutdown (TSD) for added protection. The TSD circuit monitors the die temperature and turns off the top and bottom gate drivers if an over temperature condition is detected. The internal soft- start capacitor is also discharged. This is a latched state and requires a power cycle to reset. Drivers The NCP1580 includes 1.5 A gate drivers to switch external N-Channel MOSFETs. This allows the NCP1580 to address high-power as well as low-power conversion requirements. The gate drivers also include adaptive non-overlap circuitry. The non-overlap circuitry increases efficiency, which minimizes power dissipation, by minimizing the body diode conduction time. A detailed block diagram of the non-overlap and gate drive circuitry used in the chip is shown in Figure 12. Careful selection and layout of external components is required, to realize the full benefit of the onboard drivers. The capacitors between VCC and GND and between BST and SWN must be placed as close as possible to the IC. The current paths for the TG and BG connections must be optimized. A ground plane should be placed on the closest layer for return currents to GND in order to reduce loop area and inductance in the gate drive circuit. BST UVLO FAULT TG PHASE 2V + - + - 2V VCC BG PWM OUT UVLO FAULT GND Figure 12. Block Diagram http://onsemi.com 7 NCP1580 APPLICATION SECTION Input Capacitor Selection The input capacitor has to sustain the ripple current produced during the on time of the upper MOSFET, so it must have a low ESR to minimize the losses. The RMS value of this ripple is: IinRMS + IOUT D (1 * D) , DVOUT * DISCHARGE + 2 DIOUT2 LOUT , COUT (VIN D * VOUT) where D is the duty cycle, IinRMS is the input RMS current, and IOUT is the load current. The equation reaches its maximum value with D = 0.5. Losses in the input capacitors can be calculated with the following equation: PCIN + ESRCIN IinRMS2, where VOUT-DISCHARGE is the voltage deviation of VOUT due to the effects of discharge, LOUT is the output inductor value and VIN is the input voltage. It should be noted that DVOUT-DISCHARGE and DVOUT-ESR are out of phase with each other, and the larger of these two voltages will determine the maximum deviation of the output voltage (neglecting the effect of the ESL). Inductor Selection where PCIN is the power loss in the input capacitors and ESRCIN is the effective series resistance of the input capacitance. Due to large dI/dt through the input capacitors, electrolytic or ceramics should be used. If a tantalum must be used, it must be surge protected. Otherwise, capacitor failure could occur. Calculating Input Startup Current Both mechanical and electrical considerations influence the selection of an output inductor. From a mechanical perspective, smaller inductor values generally correspond to smaller physical size. Since the inductor is often one of the largest components in the regulation system, a minimum inductor value is particularly important in space-constrained applications. From an electrical perspective, the maximum current slew rate through the output inductor for a buck regulator is given by: V * VOUT SlewRateLOUT + IN LOUT To calculate the input startup current, the following equation can be used. Iinrush + COUT VOUT , tSS where Iinrush is the input current during startup, COUT is the total output capacitance, VOUT is the desired output voltage, and tSS is the internal soft-start interval. If the inrush current is higher than the steady state input current during max load, then the input fuse should be rated accordingly, if one is used. Output Capacitor Selection The output capacitor is a basic component for the fast response of the power supply. In fact, during load transient, for the first few microseconds it supplies the current to the load. The controller immediately recognizes the load transient and sets the duty cycle to maximum, but the current slope is limited by the inductor value. During a load step transient the output voltage initially drops due to the current variation inside the capacitor and the ESR. (neglecting the effect of the effective series inductance (ESL)): DVOUT-ESR + DIOUT ESRCOUT, This equation implies that larger inductor values limit the regulator's ability to slew current through the output inductor in response to output load transients. Consequently, output capacitors must supply the load current until the inductor current reaches the output load current level. This results in larger values of output capacitance to maintain tight output voltage regulation. In contrast, smaller values of inductance increase the regulator's maximum achievable slew rate and decrease the necessary capacitance, at the expense of higher ripple current. The peak-to-peak ripple current is given by the following equation: Ipk-pkLOUT + VOUT(1 * D) LOUT 350 kHZ , where Ipk-pkLOUT is the peak to peak current of the output. From this equation it is clear that the ripple current increases as LOUT decreases, emphasizing the trade-off between dynamic response and ripple current. Feedback and Compensation where VOUT-ESR is the voltage deviation of VOUT due to the effects of ESR and the ESRCOUT is the total effective series resistance of the output capacitors. A minimum capacitor value is required to sustain the current during the load transient without discharging it. The voltage drop due to output capacitor discharge is given by the following equation: The NCP1580 allows the output of the DC-DC converter to be adjusted from 0.8 V to 5.0 V via an external resistor divider network. The controller will try to maintain 0.8 V at the feedback pin. Thus, if a resistor divider circuit was placed across the feedback pin to VOUT, the controller will regulate the output voltage proportional to the resistor divider network in order to maintain 0.8 V at the FB pin. http://onsemi.com 8 NCP1580 VOUT R1 FB R2 Figure 13. The relationship between the resistor divider network in Figure 13 and the output voltage is shown in the following equation: R2 + R1 VREF . VOUT * VREF The compensation network consists of the internal error amplifier and the impedance networks ZIN (R1, R3 and C3) and ZFB (R4, C1 and C2). The compensation network has to provide a closed loop transfer function with the highest 0 dB crossing frequency to have fast response (but always lower than fSW/8) and the highest gain in DC conditions to minimize the load regulation. A stable control loop has a gain crossing with -20 dB/decade slope and a phase margin greater than 45. Include worst-case component variations when determining phase margin. To place the poles and zeroes of the compensation networks, the following equations may be used: Modulator frequencies: w LC + 1 LOUT COUT w ESR + 1 ESR COUT Resistor R1 is selected based on a design trade off between efficiency and output voltage accuracy. For high values of R1 there is less current consumption in the feedback network, However the trade off is output voltage accuracy due to the bias current in the error amplifier. The output voltage error of this bias current can be estimated using the following equation (neglecting resistor tolerance): Error% + 0.1 mA VREF R1 100% Compensation network frequency: w P1 + R4 w Z1 + 1 R4 C2 1 1 w P2 + R3 C3 C1 C2 C1)C2 w Z2 + 1 (R1 ) R3) C3 Once R1 has been determined, R2 can be calculated. The NCP1580 utilizes voltage mode control. This is to say, the control loop regulates VOUT by monitoring VOUT and controlling the output current. However, since the control loop is controlling the output current to regulate the output voltage, there are some stability concerns since the inductor current is 90 degrees out of phase with the voltage. It is inherent with all voltage-mode control loops to have a compensation network. VIN Place wZ1, and wZ2 around the output filter resonance wLC; Place wP1 at the output capacitor ESR zero wESR; Place wP2 at one half of the switching frequency; The modulator transfer function is the small-signal transfer function of VOUT/VCOMP. This function has a double pole at frequency wLC and a zero at wESR. The DC Gain of the modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage DVOSC. Error Amplifier Closed Loop Gain LOUT VOUT wZ1 wZ2 ESR wP1 wP2 COUT C1 C2 R1 C3 R3 VRAMP - + PWM COMPARATOR wLC wESR Compensation Network R4 Figure 14. Simplified Diagram of Control Loop + - VREF R2 Modulator Gain Figure 15. Visit http://www.onsemi.com/pub/Collateral/COMPCALC for self extracting compensation program for design assistance. http://onsemi.com 9 NCP1580 Thermal Considerations The power dissipation of the NCP1580 varies with the MOSFETs used, VCC, and the boost voltage (VBST). The average MOSFET gate current typically dominates the control IC power dissipation. The IC power dissipation is determined by the formula: PIC + (ICC VCC) ) PTG ) PBG. Where: QBG = total lower MOSFET gate charge at VCC. The junction temperature of the control IC can then be calculated as: TJ + TA ) PIC qJA. Where: PIC = Control IC power dissipation, ICC = IC measured supply current, VCC = IC supply voltage, PTG = Top gate driver losses, PBG = Bottom gate driver losses. The upper (switching) MOSFET gate driver losses are: PTG + QTG fSW VBST. Where: TJ = The junction temperature of the IC, TA = The ambient temperature, qJA = The junction-to-ambient thermal resistance of the IC package. The package thermal resistance (RqJC) can be obtained from the specifications section of this data sheet and a calculation can be made to determine the IC junction temperature. In addition, a thermal resistance (Junction-to-Ambient/Safe Operating Area) curve has been included below to further aid design. However, it should be noted that the physical layout of the board, the proximity of other heat sources such as MOSFETs and inductors, and the amount of metal connected to the IC, impact the temperature of the device. Use these calculations as a guide, but measurements should be taken in the actual application. 0.570 0.595 0.645 Pd (W) (@ 25C Ambient) 0.620 0.670 0.695 1 oz cu 0.720 0.745 0.770 0.795 Where: QTG = Total upper MOSFET gate charge at VBST, fSW = The switching frequency, VBST = The BST pin voltage. The lower (synchronous) MOSFET gate driver losses are: PBG + QBG fSW 175 165 155 qJA (C/W) 145 135 125 115 0 2 oz cu VCC. 0.820 0.845 0.870 50 100 150 200 250 300 350 400 450 500 550 600 650 Copper Area (mm2) Figure 16. Thermal Resistance (Junction-to-Ambient/Safe Operating Area) http://onsemi.com 10 NCP1580 Layout Considerations VIN As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible using ground plane construction or single point grounding. Figure 17 shows the critical power components of the converter. To minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. The components shown in Figure 17 should be located as close together as possible. Please note that the capacitors CIN and COUT each represent numerous physical capacitors. It is desirable to locate the NCP1580 within 1 inch of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs' gate and source connections from the NCP1580 must be sized to handle up to 2.0 A peak current. Q1 TG PHASE NCP1580 Q2 BG GND RETURN R1 D2 CIN COUT LOUT VOUT LOAD Figure 17. http://onsemi.com 11 NCP1580 PACKAGE DIMENSIONS SOIC-8 D SUFFIX CASE 751-07 ISSUE AD -X- A 8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 B 1 4 S 0.25 (0.010) M Y M -Y- G C -Z- H D 0.25 (0.010) M SEATING PLANE K N X 45 _ 0.10 (0.004) M J ZY S X S DIM A B C D G H J K M N S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 12 NCP1580/D |
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